1. Technical Field
The present invention is directed to an improved data processing system and in particular for improving data cache control instructions for utilization in a data processing system. Still more particularly the present invention relates to an improved method for efficient execution of cache control instructions which operates on less bytes than the coherency granule in a Symmetrical Multiprocessing (SMP) System.
2. Description of the Related Art
Many systems for processing information include both a system memory and a cache memory. A cache memory is a relatively small, high-speed memory that stores a copy of information from one or more portions of the system memory. Frequently, the cache memory is physically distinct from the system memory. Such a cache memory can be integral with the processor device of the system (referred to as an L1 cache) or non-integral with the processor (referred to as an L2 cache).
Information may be copied from a portion of the system memory into the cache memory. The information in the cache memory may then be modified. Further, modified information from the cache memory can then be copied back to a portion of the system memory. Accordingly, it is important to map information in the cache memory relative to its location within system memory. Assuming selection of an appropriately sized cache memory and the efficient storage of data therein the limiting factor in cache performance is the speed of the cache memory and the ability of the system to rapidly read data from the cache memory.
In addition to using a cache memory to retrieve data, the processor may also write data directly to the cache memory instead of to the system memory. When the processor desires to write data to memory, an address tag comparison is made to determine whether the line into which data is to be written resides in the cache memory. If the line is present in the cache memory, the data is written directly into the line. This event is referred to as a cache write "hit". If the line into which data is to be written does not exist in the cache memory, the line is either fetched into the cache memory from system memory to allow the data to be written into the cache, or the data is written directly into the system memory. This event is referred to as a cache write, "miss."
In today's fast growing microprocessor environment, backward compatibility and the ability to run existing operating systems has become a requirement. Cache control operations, most of which are privileged instructions fall under the category of requirements that must be aligned with the existing operating systems when reading or writing into cache. There are many implications to a cache organization and control with differing cache control instruction target blocks and coherency granule size that have to be taken into consideration. This is especially true of cache control operations that are visible to the software.
In prior 32-bit PowerPC microprocessors, the processors supported 32-byte cache control instructions with a 32-byte coherency granule. However, in today's modern higher performance 32-bit microprocessor design the bus supports more than 32 byte transfers, and reads more than 32 bytes from memory. In modern processors the cache block size is at least 64 bytes, but must have the ability to write and manipulate 32 byte portions within a block. Therefore there is a need for a cache structure/control that provides an efficient method for handling the cases that arise when supporting cache control operations which affect less bytes than the coherency granule and is flexible enough to accommodate all other normal operations that are commonly performed to a cache in a processor with SMP support.
In view of the above, it should be apparent that a method and system for addressing any combination of greater coherency granules than the target of cache control instructions used by a given operating system would be highly desirable.